[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Tom Dillon wrote:
> Jan,
> 
> That works great, I use it with the following code:
> 
>  memL = [intbv(0,min=dout._min,max=dout._max) for i in range(depth)]
>    while 1:
>        yield posedge(clk)
>        if we:
>          memL[int(addr)][:] = din
>          # print "ram: wrote %d to %d"%(din,addr)
>        dout.next = memL[int(addr)]
> 
> This synthesized into Virtex blockRAM using Mentor Precision just fine.

Ok. The code was committed to the next release.

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