Re: [myhdl-list] Re: toVerilog and memories

[<dan...@we...>]

Hello,

Tom Dillon wrote:

...


> 
> For a true dual port (dual clock) we need something like the following:
> 
>    reg [7:0] mem [31:0];
> 
>    always @(posedge write_clock)
>        if (wea)
>            mem[addr_write] <= data_in;
> 
>    always @(posedge read_clock)
>        data_out <= mem[addr_read];
> 
> Tom

I tried to implement a dual-port RAM with synchronous read. The Xilinx
XST manual provides a Verilog template for that. Basically if the XST
finds a Verilog construct in the form of that template, it will
implement it as a dual-port RAM.

Following is the Verilog code for a dual-port RAM with synchronous read
(read through).

module raminfr (clk, we, a, dpra, di, spo, dpo);
input clk;
input we;
input [4:0] a;
input [4:0] dpra;
input [3:0] di;
output [3:0] spo;
output [3:0] dpo;

reg [3:0] ram [31:0];
reg [4:0] read_a;
reg [4:0] read_dpra;

always @(posedge clk) begin

  if (we)
    ram[a] <= di;
    read_a <= a;
    read_dpra <= dpra;
  end

  assign spo = ram[read_a];
  assign dpo = ram[read_dpra];

endmodule


Now I tried to implement that in myhdl so that toVerilog would create
the respective Verilog.

My show stopper was that I did not really know how to implement the
assign statement. I searched through the mailing list archive and found
a post from March 2nd of this year with the subject "syntax sugar?" from
Haitao Zhang.

He wrote:

> assign a = expr
> 
> In myhdl one has to do
> def assign_blk():
>     while 1:
>         yield signals in expr
>         a.next = expr
> 
> or:
> def assign_blk():
>     def blk():
>         a.next = expr
>     return always_comb(blk)
> 
> AND one needs to keep track of all the generators:
> assign_blk_list.append(assign_blk())

First that looked simple, just implement it as combinatorial logic, but
then there is that comment about needing to keep track of the generators
that I did not understand. Maybe somebody can give me some explanation
about why I need to keep track of the generators? Does it not work as a
combinatorial logic implementation by itself?

I tried to go on, without considering the assign statement for now and
ran into another issue with the two read_* registers.

Below is my myhdl code. When doing it as below I have the problem, that
toVerilog specifies the registers inside the always statement. I
commented about that already yesterday with the memory array. I tried to
avoid that by explicit initializing the python variables outside the
while loop, which is now commented out. But that only brought me a type
mismatch error message, probably because I am passing a signal to the
dp_ram_py() function.


def dp_ram_py(clk, we, addr, di, spo, dp_addr, dpo):

  memL = [intbv(0)[d_width:] for i in range(a_width^2)]

  #read_addr = intbv(0)[a_width:]
  #read_dp_addr = intbv(0)[a_width:]

  while 1:
    yield posedge(clk)

    if we:
      memL[int(addr.val)][:] = di.val

    read_addr = addr
    read_dp_addr = dp_addr

    spo.next = memL[int(read_addr.val)]
    dpo.next = memL[int(read_dp_addr.val)]



I would appreciate any help how to solve that.

Thanks in advance.

Guenter