Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

>The first thing ISE tripped over was that the memL array is inside the
>always statement. Moving it out from there made it go on, but then there
>is a blocking and nonblocking assignment inside the always statement and
>that one it did not like either.
>
>Is it possible to change that with the toVerilog conversion?
>
>  
>
Guenter makes a good point here. We will actually need the array to be 
defined outside the always block and accessible from multiple always blocks.

For a true dual port (dual clock) we need something like the following:

    reg [7:0] mem [31:0];

    always @(posedge write_clock)
        if (wea)
            mem[addr_write] <= data_in;

    always @(posedge read_clock)
        data_out <= mem[addr_read];

Tom