Re: [myhdl-list] Re: toVerilog and memories

[<dan...@we...>]

Jan,

I tried a simple example with the memory and to implement it with ISE
6.3, but ran into some problems. I am not sure whether I did something
wrong how I wrote the MyHDL code or need to do some special ISE
settings? I basically pulled in the generated Verilog file into a ISE
project with the standard settings and ran it through implementation.

Here is the MyHDL code that I used:


def ram(clk, dout, din, addr, we, d_width=8, depth=4) :

  memL = [intbv(0)[d_width:] for i in range(depth)]

  while 1:
    yield posedge(clk)

    if we:
      memL[int(addr.val)][:] = din.val

    dout.next = memL[int(addr.val)]




and that is the generated Verilog code:


module inst_ram (
    clk,
    dout,
    din,
    addr,
    we
);

input [0:0] clk;
output [7:0] dout;
reg [7:0] dout;
input [7:0] din;
input [1:0] addr;
input we;



always @(posedge clk) begin: _MYHDL1_BLOCK
    reg [8-1:0] memL [0:4-1];
    if (we) begin
        memL[addr] = din;
    end
    dout <= memL[addr];
end

endmodule


The first thing ISE tripped over was that the memL array is inside the
always statement. Moving it out from there made it go on, but then there
is a blocking and nonblocking assignment inside the always statement and
that one it did not like either.

Is it possible to change that with the toVerilog conversion?

I also recognized that the 'clk' signal is specified as input [0:0]
whereas the 'we' signal is specified only as input.


Regards

Guenter




Jan Decaluwe wrote:
> Jan Decaluwe wrote:
> 
>> Here is my proposed plan:
>>
>> I will work on an implementation of list comprehensions mapped to
>> Verilog memories, along the lines described om my previous mail. I´ll
>> post an alpha release to the newsgroup for you and others to test it
>> before committing it to the next release.
> 
> 
> Attached you find a patch to MyHDL to support Verilog memories.
> 
> A list comprehension with intbv elements in a generator is
> converted to a Verilog memory.
> 
> To install the patch, replace the myhdl/_toVerilog directory
> in a 0.4.1 installation by the attached directory.
> 
> There are several constraints, but I'm not providing an example
> in order to ensure that the error handling is tested also :-)
> 
> Regards,
> 
> Jan
>