Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

Jan,

That works great, I use it with the following code:

  memL =3D [intbv(0,min=3Ddout._min,max=3Ddout._max) for i in range(depth=
)]
  =20
  while 1:
        yield posedge(clk)
        if we:
          memL[int(addr)][:] =3D din
          # print "ram: wrote %d to %d"%(din,addr)
        dout.next =3D memL[int(addr)]

This synthesized into Virtex blockRAM using Mentor Precision just fine.

Now, I should have thought of this earlier, but I am working=20
sequentially here.

ROMs are also needed and easy to infer in synthesis. It would be very=20
good if the following would produce a case statement in Verilog:

def rom(dout,addr,clk=3DNone,dataL=3DNone) :
  """
    rom : rom module

    Inputs:
      addr        : input address
      clk         : clock for synchronous roms, =3D=3D None for async
    Outputs:
      dout        : output port, width determines width of rom
    Params:
      dataL       : list of values for rom, length is depth of rom
  """

  memL =3D [intbv(data,min=3Ddout._min,max=3Ddout._max) for data in dataL=
]
  =20
  while 1:
        yield posedge(clk)
        dout.next =3D memL[int(addr)]


You would need to be able to figure out that the values in memL never=20
get modified after it is defined.

The important thing here, is the memL define and the dout.next=20
assignment need to get mapped to a case statement:

always @(posedge clk)
  case(addr) :
    0 : dout <=3D dataL[0] ;
    1 : dout <=3D dataL[1] ;
    .
    .
    .

This also works in XST.

Now you may also want some control around this, or possibly asynchronous=20
so only the list needs to become the case statement, that case statement=20
may end up inside come control statements. Possibly a clock enable.

This is very helpful. There are also dual port ROMs, so you would need=20
two case statements on the same list, with a separate address into the li=
st.

You  can also initialize the values of a RAM. This is more obscure and=20
I've never actually used it. But it too can be inferred from HDL. I will=20
forward the coding style when I find it. I could not find it today.

Anyhow, thanks for the help thus far on the memories and let me know=20
what you think of the rom idea.

Tom





=20

Jan Decaluwe wrote:

> Jan Decaluwe wrote:
>
>> Here is my proposed plan:
>>
>> I will work on an implementation of list comprehensions mapped to
>> Verilog memories, along the lines described om my previous mail. I=B4l=
l
>> post an alpha release to the newsgroup for you and others to test it
>> before committing it to the next release.
>
>
> Attached you find a patch to MyHDL to support Verilog memories.
>
> A list comprehension with intbv elements in a generator is
> converted to a Verilog memory.
>
> To install the patch, replace the myhdl/_toVerilog directory
> in a 0.4.1 installation by the attached directory.
>
> There are several constraints, but I'm not providing an example
> in order to ensure that the error handling is tested also :-)
>
> Regards,
>
> Jan
>