[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:

> Here is my proposed plan:
> 
> I will work on an implementation of list comprehensions mapped to
> Verilog memories, along the lines described om my previous mail. I´ll
> post an alpha release to the newsgroup for you and others to test it
> before committing it to the next release.

Attached you find a patch to MyHDL to support Verilog memories.

A list comprehension with intbv elements in a generator is
converted to a Verilog memory.

To install the patch, replace the myhdl/_toVerilog directory
in a 0.4.1 installation by the attached directory.

There are several constraints, but I'm not providing an example
in order to ensure that the error handling is tested also :-)

Regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
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