Re: [myhdl-list] Re: Opencores project

[<dan...@we...>]

Jan,

Jan Decaluwe wrote:

...

> In a project of certain complexity, it is normal to find 2
> levels of modeling:
> 
> 1. a very high level reference model. This is a model to
> experiment with algorithms and architectures, with little
> concern for implementation details. MyHDL should be a
> good choice here. Others may use C, C++, SystemC, Matlab,
> perl ...
> 
> 2. an implementation-oriented model. Used to synthesize or
> define the implementation. Typically done in Verilog or VHDL.
> 
> I think this matches what you have done in your project.

...

> In short, one would still have to write 2 models, but both could
> be in MyHDL. However, learning about the ´´synthesizable subset´´
> will still be unavoidable for type 2 modeling.
> 

That approach has the disadvantage that 2 separate models have to be
done. I think MyHDL has the potential to combine that and that would be
a great benefit as it could speed up the development process.

Just as one example, there are numerous math functions available for
python that makes it in some cases a perfect substitute for Matlab.


> If we agree on the above, we can consider the feature set.

I agree on that, but would like to discuss a 3. feature and that is some
kind of framework that allows to merge the 2 features.

...

> 
> The suggested approach to improve things is one feature at a time.
> Start a discussion on the most pressing feature, with a rationale
> and a small example. The more specific, the better.
> The current discussion on Verilog memories is a good example.
> 
> Regards, Jan
> 

I agree, that first two features need to be set in order to add the
third idea. I would like to describe it here, in order to see whether it
is really feasible.

My idea is to have some type of framework class, that is the basic
building block to model with MyHDL. Instead of using functions that
resemble modules in Verilog my suggestion would be to use classes.

To model, one would derive a class from the framework class, which
provides predefined member functions that need to be filled with logic.

One member function is for the *behavioral* modeling and is used to do
the higher layer modeling. Level 1 as you called it.

So it is possible to model just with that, create instances of the class
and run it with the MyHDL simulator as before.


The merge would come from a second member function that allows to do the
*rtl* or level 2 modeling. In that member function it is possible to
model the logic in a way that it can be converted with toVerilog and
create synthesizable logic.

The advantage from that approach would be that behavioral and rtl
modeling are close together, grouped together in an object oriented
manner. That would allow to do verification on the individual class
instances.

One idea would be for example that there is a third member function that
allows to run the simulation of the behavioral model, take data from
that and compare it with co-simulation results of the toVerilog code.

Now I am not that experienced with MyHDL and logic development in
general to know what an effort that proposed framework would be. Also I
am not sure whether classes would become too complex, as it would hold
behavioral, rtl modeling and verification code.

It would be interesting to hear some of your thoughts about this idea.


Regards,

Guenter