[myhdl-list] Re: Opencores project

[Jan D. <ja...@ja...>]

David Brochart wrote:

> From my experience the current toVerilog cannot be used in a real project. But
> it can be easily improved by adding more and more features.

It could be either expectations that are too high, or a
feature set that is too small. I would like to find that
out, so to avoid any misunderstandings I´ll first describe
my view on the role of toVerilog in a real project.

In a project of certain complexity, it is normal to find 2
levels of modeling:

1. a very high level reference model. This is a model to
experiment with algorithms and architectures, with little
concern for implementation details. MyHDL should be a
good choice here. Others may use C, C++, SystemC, Matlab,
perl ...

2. an implementation-oriented model. Used to synthesize or
define the implementation. Typically done in Verilog or VHDL.

I think this matches what you have done in your project.

The role of toVerilog is not to convert a type 1 model into
a type 2 model. Considering the extreme power of Python
(which is very useful for type 1 modeling) this seems like
an impossible task.

Rather, the purpose of toVerilog is that the type 2 model
can *also* be written in MyHDL, instead of having to use
another language. Potential benefits: familiar language,
partial reuse of code and verification environment, potentially
several backends (Verilog, VHDL) from a single code base.

In short, one would still have to write 2 models, but both could
be in MyHDL. However, learning about the ´´synthesizable subset´´
will still be unavoidable for type 2 modeling.

If we agree on the above, we can consider the feature set.
I have not done any real projects myself with MyHDL or toVerilog,
so I cannot judge wether the feature set is sufficient, although
the intention with the release was that it would be. On the
other hand, I´m pretty sure that I would also encounter difficulties
in a real project.

The suggested approach to improve things is one feature at a time.
Start a discussion on the most pressing feature, with a rationale
and a small example. The more specific, the better.
The current discussion on Verilog memories is a good example.

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
     Using Python as a hardware description language:
     http://jandecaluwe.com/Tools/MyHDL/Overview.html