[myhdl-list] Re: Opencores project

[Jan D. <ja...@ja...>]

David Brochart wrote:
> Günter,
> 
> Yes, I started from the toVerilog for the toVHDL convertor. It is quite easy to
> identify where to replace the Verilog generated code with the VHDL generated
> code. But the thing is that MyHDL looks like Verilog in its structure, and VHDL
> is quite different, so that is where the difficulty is.

If it looks more like Verilog, that´s certainly not the intention :-)

For crucial features, the main inspiration has been VHDL, for example
the delta-cycle algorithm, the strict separation between signals and
variables, strong typing (thanks to Python of course), ...

However, I certainly believe that writing toVHDL by starting from
toVerilog is difficult. Here are two considerations:

- Verilog is a lower level language, with loose typing. This may
make it easier in the direction from MyHDL to Verilog. Easier,
because they are more different, in this case :-)

- the main reason is probably that toVerilog has code that may
*seem* generic, but isn´t. In the ideal case, there would be a
generic analyzer, with just a dedicated backend in the conversion
stage. However, that´s not the case. The whole thing was certainly
written with Verilog in mind. If I would write toVHDL, I would start
from scratch (benefiting from the toVerilog experience, of course.)

Regards,

Jan

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