[myhdl-list] Black box discussion
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From: Tom D. <td...@di...> - 2005-07-09 19:02:35
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OK, here is my start to a black box implementation discussion.
>
> I=B4ll think about the black box feature. It would really be useful
> though to start a discussion here about the details of such a feature
> (in a new thread). Getting a well thought-out, detailed spec is a large
> part of the solution! To get started, some issues to consider:
> - what should the user interface be exactly (as simple as possible)
> - how to handle parameters
>
>
For the interface I would propose something like this:
portD =3D {'xPort':xSig,'aPort':aSig,'bPort':bSig}
parmD =3D {'parm1':num1,'parm2':num2}
blackBox('modName','instName',portD,partD)
modName is the module name you are connecting to, instName the instance=20
name, both just strings. Then just the port dictionary, connects MyHDL=20
signals (xSig,aSig,bSig) to the port names. Same with the parameter=20
dictionary. num1 and num2 are both python numbers, but could be=20
anything, just needs to be turned into a string.
blackBox() is a MyHDL function. The MyHDL source that contains this=20
would need to knwo toVerilog was running and substitute the blackBox()=20
for the behavior model used during MyHDL simulation.
What we need on the Verilog side is:
modName #(
.parm1(num1),
.parm2(num2)
) instName (
.xPort(xSig),
.aPort(aSig),
.bPort(bSig)
)
I think that would do it, but I probably have not thought this all the=20
way through.
Tom
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