Re: [myhdl-list] Re: toVerilog and memories

[Tom D. <td...@di...>]

Jan,

> Are verilog memories actually synthesized by your synthesis tool (and
> which is it)? I don=B4t know of an ASIC tool that has this, though I
> see how this could work for FPGAs. That would be very useful of
> course, and a strong argument to support it.


Yes, we use Mentor Precision and it works very well. It will infer all=20
kinds of memory structures and map to the appropriate FPGA memory. It=20
keeps the source more or less generic and makes the synthesis tool do=20
the work.

>
> Here is my proposed plan:
>
> I will work on an implementation of list comprehensions mapped to
> Verilog memories, along the lines described om my previous mail. I=B4ll
> post an alpha release to the newsgroup for you and others to test it
> before committing it to the next release.
>
> Give me a few days (can=B4t start before Tuesday) - if it takes longer
> I=B4ll post about the progress.


Sounds great. Let me know if you need any help.

Tom