[myhdl-list] Re: Opencores project

[David B. <dav...@fr...>]

G=FCnter,

Yes, I started from the toVerilog for the toVHDL convertor. It is quite e=
asy to
identify where to replace the Verilog generated code with the VHDL genera=
ted
code. But the thing is that MyHDL looks like Verilog in its structure, an=
d VHDL
is quite different, so that is where the difficulty is.

Regards,

David.



Selon G=FCnter Dannoritzer <dan...@we...>:

> David,
>
> David Brochart wrote:
>
> ...
>
> > (multi-dimensional arrays, list of instanciations...). I started writ=
ing a
> > toVHDL equivalent to toVerilog because I know what I want to be trans=
lated
> and
> > I'm more familiar in VHDL than in Verilog, but I'm not finished with =
it
> ...
>
> That is great, so there is a toVHDL in progress.
>
> > Also, my toVHDL translator was
> > not so clean and as Jan said, it is important to start with a clean s=
pec of
> the
> > things that should be translated and the things that should not. So I=
 will
> need
> > to spend more time on the toVHDL translator.
>
> Did you start out with the toVerilog? I was reading a bit how the
> toVerilog works and I was wondering whether a quick trick would be to
> take the part that generates the Verilog code and just replace it by
> VHDL. But I guess I am not that experienced with VHDL and Verilog to se=
e
> whether that really would go that easy.
>
>
> >>From my experience the current toVerilog cannot be used in a real pro=
ject.
> But
> > it can be easily improved by adding more and more features.
> >
> > Regards,
> >
> > David.
> >
>
> Thanks for sharing that.
>
> Guenter
>
>
>
> ...
>
>
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