[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

Tom Dillon wrote:

> To use MyHDL effectively for making logic, I would like to be able to 
> synthesize the Verilog generated, that is my real end goal. So I would 
> really add the requirement that the subset of Verilog used was 
> synthesizable by a decent FPGA synthesis tool.

I agree completely, it should even be a superset. (In some areas,
it already is in fact.)

Are verilog memories actually synthesized by your synthesis tool (and
which is it)? I don´t know of an ASIC tool that has this, though I
see how this could work for FPGAs. That would be very useful of
course, and a strong argument to support it.

> Alternatively, and really needed as well, is a way to include a black 
> box into the simulation(Verilog)/synthesis flow. So you would use a 
> MyHDL function for behavioral MyHDL simulation, then substitute in a 
> block box when either doing co-simulation or synthesis. Possible an 
> attribute on the function or something to trigger this.

I agree that this is needed also. I had been thinking about it, but
I haven´t tackled the details.

> I am still really just experimenting with MyHDL but am trying to take 
> some our real logic there to give it a test drive. It is working well, 
> but there isn't much we build that doesn't have memories inside the FPGA.
> 
> Any ideas on how hard it is to implement a black box type connection? 
> That would keep me on my experimentation path and give me a way to solve 
> anything later too. You just need module name, signal connections, and 
> parameters.
> 
> Anyhow, I'm willing to help make changes or test or do whatever I can. 
> Let me know.

Here is my proposed plan:

I will work on an implementation of list comprehensions mapped to
Verilog memories, along the lines described om my previous mail. I´ll
post an alpha release to the newsgroup for you and others to test it
before committing it to the next release.

Give me a few days (can´t start before Tuesday) - if it takes longer
I´ll post about the progress.

I´ll think about the black box feature. It would really be useful
though to start a discussion here about the details of such a feature
(in a new thread). Getting a well thought-out, detailed spec is a large
part of the solution! To get started, some issues to consider:
- what should the user interface be exactly (as simple as possible)
- how to handle parameters

Regards,

Jan

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Jan Decaluwe - Resources bvba - http://jandecaluwe.com
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