Re: [myhdl-list] Re: Opencores project

[<dan...@we...>]

David,

David Brochart wrote:

...

> (multi-dimensional arrays, list of instanciations...). I started writing a
> toVHDL equivalent to toVerilog because I know what I want to be translated and
> I'm more familiar in VHDL than in Verilog, but I'm not finished with it 
...

That is great, so there is a toVHDL in progress.

> Also, my toVHDL translator was
> not so clean and as Jan said, it is important to start with a clean spec of the
> things that should be translated and the things that should not. So I will need
> to spend more time on the toVHDL translator.

Did you start out with the toVerilog? I was reading a bit how the
toVerilog works and I was wondering whether a quick trick would be to
take the part that generates the Verilog code and just replace it by
VHDL. But I guess I am not that experienced with VHDL and Verilog to see
whether that really would go that easy.


>>From my experience the current toVerilog cannot be used in a real project. But
> it can be easily improved by adding more and more features.
> 
> Regards,
> 
> David.
> 

Thanks for sharing that.

Guenter



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