[myhdl-list] Re: toVerilog and memories

[Jan D. <ja...@ja...>]

David Brochart wrote:
> Tom,
> 
> In order to fix the error message on addr, replace memL[addr] with
> memL[int(addr.val)].
> Unfortunately the current version of the Verilog translator doesn't support
> signal list (array) translation.
> Jan, do you plan to support it in the next release(s)?

I understand the need and I think it´s possible to support
a limited form of list comprehensions. There are a number
of (Verilog-related) issues though that have to be resolved,
so we need to think carefully first and come up with a
good spec. I will give the start by replying in detail
to Tom´s original mail - stay tuned.

Jan

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