[myhdl-list] Re: Opencores project

[Guenter D. <dan...@we...>]

David Brochart wrote:

> All,
> 
> I have posted a project on Opencores. It is a MyHDL model of a turbo decoder,
> still at an early stage of development. You might want to check it out at:
> http://www.opencores.org/projects/turbocodes/
> 
> Regards,
> 
> David.
> 

David,

I looked into you project to study MyHDL and recognized that there is
some toVerilog usage, but in the description it does not say anything
that the MyHDL implementation is able to generate Verilog code. Also you
added the VHDL synthesizeable code.

Did you need the code in VHDL or was there some other reason not to use
the toVerilog?

From you experience how well can the toVerilog be used to generate
Verilog code?

I saw in a different thread that it is not possible to generate lists of
Signals. Is there a different way to model Verilog generateable memory?

Thanks for you thoughts.

Guenter