Re: [myhdl-list] toVerilog and memories

[Tom D. <td...@di...>]

David,

Thanks, I had that part figured out and that made it work in myhdl 
simulation.

I was looking into the _toVerilog code to see how difficult it would be 
to add support but haven't spent enough time on it yet. I have never 
used python code generation so it is all a little new to me but very 
interesting.

Thanks, Tom


David Brochart wrote:

>Tom,
>
>In order to fix the error message on addr, replace memL[addr] with
>memL[int(addr.val)].
>Unfortunately the current version of the Verilog translator doesn't support
>signal list (array) translation.
>Jan, do you plan to support it in the next release(s)?
>
>Regards,
>
>David.
>
>
>
>Selon Tom Dillon <td...@di...>:
>
>  
>
>>I am trying to model generate Verilog for some simple memories. For example:
>>
>>def ram(dout,din,addr,we,clk=None,depth=4) :
>>  memL = [Signal(intbv(0,min=0,max=2**8)) for i in range(depth)]
>>
>>  while 1:
>>    yield posedge(clk)
>>    if we:
>>      memL[addr] = din.val
>>    dout.next = memL[addr]
>>
>>I want addr to be a Signal as well. I get an error that it needs to be
>>an int.
>>
>>If I use the value of addr, then it simulates fine but I get a list
>>comprehension error when running it through toVerilog.
>>
>>Is there a way to do this and get it through toVerilog?
>>
>>Thanks, Tom
>>
>>
>>
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