Re: [myhdl-list] toVerilog and memories

[David B. <dav...@fr...>]

Tom,

In order to fix the error message on addr, replace memL[addr] with
memL[int(addr.val)].
Unfortunately the current version of the Verilog translator doesn't suppo=
rt
signal list (array) translation.
Jan, do you plan to support it in the next release(s)?

Regards,

David.



Selon Tom Dillon <td...@di...>:

> I am trying to model generate Verilog for some simple memories. For exa=
mple:
>
> def ram(dout,din,addr,we,clk=3DNone,depth=3D4) :
>   memL =3D [Signal(intbv(0,min=3D0,max=3D2**8)) for i in range(depth)]
>
>   while 1:
>     yield posedge(clk)
>     if we:
>       memL[addr] =3D din.val
>     dout.next =3D memL[addr]
>
> I want addr to be a Signal as well. I get an error that it needs to be
> an int.
>
> If I use the value of addr, then it simulates fine but I get a list
> comprehension error when running it through toVerilog.
>
> Is there a way to do this and get it through toVerilog?
>
> Thanks, Tom
>
>
>
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