[myhdl-list] toVerilog and memories

[Tom D. <td...@di...>]

I am trying to model generate Verilog for some simple memories. For example:

def ram(dout,din,addr,we,clk=None,depth=4) :
  memL = [Signal(intbv(0,min=0,max=2**8)) for i in range(depth)]
   
  while 1:
    yield posedge(clk)
    if we:
      memL[addr] = din.val
    dout.next = memL[addr]

I want addr to be a Signal as well. I get an error that it needs to be 
an int.

If I use the value of addr, then it simulates fine but I get a list 
comprehension error when running it through toVerilog.

Is there a way to do this and get it through toVerilog?

Thanks, Tom