[myhdl-list] Re: inference problem?

[Jan D. <ja...@ja...>]

Haitao Zhang wrote:
> Thanks for the explaination. There seems to be a little more to it:
> toVerilog does not always flag different  port name and signal name as
> a problem (e.g. the q signal for the q3 port was fine). It actually
> seemed content to let most pass but somehow caught on to the
> particular example I gave. 

Haitao:

Nice debugging work! To explain what happens, consider the following:

>>> from myhdl import *
>>> q = Signal(0)
>>> def f(q3):
...     return q is q3
...
>>> f(q)
True

The point is that inside f, q and q3 can now be used interchangeably.
This is of course utterly confusing, but if you did write code
like that, MyHDL can still generate correct Verilog code! (ain't it great?)
It will choose one of the 2 names (q or q3) and use it consistently.
However, if it chooses the one different from the port name, toVerilog
will fail for the reason described in an earlier mail.

Currently, the name choice is arbitrary, based on the occurence of
the names/Signals in a dictionary. (Warning: seemingly unrelated
statements can influence this - However: when the conversion
works, it should be correct :-)) What it should do is always use
the port name (as per the feedback I received, and I agree.)

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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