[myhdl-list] Re: inference problem?

[David B. <dav...@fr...>]

> Conclusion: in any case, the current error is misleading
> for the situation you encounter. This has to be solved.
> There are 3 options, and I ask for feedback:
>
> - top level signal names should be the same as their
> corresponding top level port names (as currently), and
> a clear error should be raised in the other case.

It means we need to change the Python code from a pure simulation use to =
a
Verilog generation use if top level signal names and top level port names=
 were
different. It would be nice not to have to do this.

> - in the generated Verilog, the MyHDL port names should be
> used.

I think it is what we expect it to do.

> - in the generated Verilog, the actual MyHDL signal names
> should be used. In this case, the Verilog module interface
> will use different port names than the MyHDL function.

I think this would lead to confusion between the MyHDL description and th=
e
Verilog description.



Regards,

David.