[myhdl-list] Re: inference problem?

[Jan D. <ja...@ja...>]

Haitao Zhang wrote:
> More challenge if you are still there:). This time I did simulate (but
> I haven't stepped throuigh toVerilog failure yet). The code simulates
> (here q2 has been defined globally):
> 
> def reg_dq3(clk,d0,q3):
>     reg1=reg_dq2(clk,d0,q2)
>     reg2=reg_dq(clk,q2,q3)
>     return reg1,reg2
> 
> If I do toVerilog like this:
> my_delay2=toVerilog(reg_dq3, clk, d0, q)
> 
> it works. But if I change it to:
> my_delay2=toVerilog(reg_dq3, clk, cntr_out, q)
> 
> toVerilog complains about shadowing. What is shadowing?

Shadowing refers to the following situation:

def top(a, b, c, ...):
   a = Signal(...)
   ...

In other words, an internal Signal "shadows" a port with the
a same name. This is perfectly valid (though meaningless) in
Python, but cannot be converted into meaningful Verilog. MyHDL
attempts to detect this, and raises a error.

What you describe is something else:

a1 = Signal(a, b, c, ...):

def top(a, b, c):
    ...

instance = toVerilog(top, a1, b, c, ...)

In other words, you use a different name for the Signal
than for the port at instantiation time. This is perfectly
valid Python and MyHDL, and could be converted into
meaningful Verilog. However, the current port name test
is too severe and detects this situation also, apart
from the real "shadowing" case.

Conclusion: in any case, the current error is misleading
for the situation you encounter. This has to be solved.
There are 3 options, and I ask for feedback:

- top level signal names should be the same as their
corresponding top level port names (as currently), and
a clear error should be raised in the other case.
- in the generated Verilog, the MyHDL port names should be
used.
- in the generated Verilog, the actual MyHDL signal names
should be used. In this case, the Verilog module interface
will use different port names than the MyHDL function.

Jan









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