Re: [myhdl-list] Re: inference problem?

[Haitao Z. <ha...@gm...>]

More challenge if you are still there:). This time I did simulate (but
I haven't stepped throuigh toVerilog failure yet). The code simulates
(here q2 has been defined globally):

def reg_dq3(clk,d0,q3):
    reg1=reg_dq2(clk,d0,q2)
    reg2=reg_dq(clk,q2,q3)
    return reg1,reg2

If I do toVerilog like this:
my_delay2=toVerilog(reg_dq3, clk, d0, q)

it works. But if I change it to:
my_delay2=toVerilog(reg_dq3, clk, cntr_out, q)

toVerilog complains about shadowing. What is shadowing? Here is the trace:

cntr_out
d0
Traceback (most recent call last):
  File "./myhdl_test.py", line 20, in ?
    my_delay2=toVerilog(reg_dq3, clk, cntr_out, q)
  File "/usr/local/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py",
line 92, in toVerilog
    _writeModuleHeader(vfile, intf)
  File "/usr/local/lib/python2.4/site-packages/myhdl/_toVerilog/_convert.py",
line 122, in _writeModuleHeader
    raise ToVerilogError(_error.ShadowingSignal, portname)
myhdl.ToVerilogError: Port is shadowed by internal signal: d0


On Sat, 26 Feb 2005 14:13:52 -0800, Haitao Zhang <ha...@gm...> wrote:
> Jan,
> Thanks! You spotted the problem!
> 
> > Yes, I infer that you didn't simulate this :-)
> 
> Right I didn't on this one. I want to build a model of my project in
> myhdl and before doing it I  wanted to be sure that it can be
> converted so I am experimenting a bit to see how things go. I did try
> some other sims just not thought of doing it here. As you can tell I
> am new to myhdl, and also pretty new to Python. Thanks for all the
> good advice.
> 
> Haitao