[myhdl-list] Re: inference problem?

[Jan D. <ja...@ja...>]

Haitao Zhang wrote:
> I could not figure out why the following code could not generate
> correct Verilog code (the intermediate q1 is missing):
> 
> def reg_dq(clk,d,q):
>     def proc():
>         while 1:
>             yield posedge(clk)
>             q.next=d
>     return proc()
>     
> def reg_dq2(clk,d,q):
>     if d._nrbits:
>         q1=Signal(intbv(0))[d._nrbits:]
>     else:
>         q1=Signal(intbv(0))
>     def proc():
>         while 1:
>             yield posedge(clk)
>             q.next=q1
>             q1.next=d
>     return proc()        
> #    reg1=reg_dq(clk,d,q1)
> #    reg2=reg_dq(clk,q1,q)
> #    return reg1, reg2
> 
> I fail to see the difference between this and the provided examples.
> This is just a simple try to generate a delay of 2. The commented out
> code didn't work either. I get two assignments to q instead.
> 
> Thanks for any help. 

Yes, I infer that you didn't simulate this :-)

Here's the problem: your intention is that q1 is a Signal, but it isn't.
In fact, in MyHDL:

   q1 = Signal(intbv(0))[n:]

is equivalent to:

   q1 = Signal(intbv(0)).val[n:]

that is, you get a slice of the current underlying value, which is an
intbv and not a signal.

What you want is:

   q1 = Signal(intbv(0)[n:])

In this case, you get a signal with an intbv (with a defined bit width)
as its underlying value.

The reason why conversion currently behaves like it does has to do
with namespace lookups. Perhaps more could be done to detect flaws,
BUT in a Python context this is an upfront battle. You really should
use the run-time (= simulation) to detect errors. I have written
about this before:

(from the manual, section 6.5.1)
"""
In the Python philosophy, the run-time rules. The Python compiler
doesn't attempt to detect a lot of errors beyond syntax errors, which
given Python's ultra-dynamic nature would be an almost impossible task
anyway. To verify a Python program, one should run it, preferably
using unit testing to verify each feature.

The same philosophy should be used when converting a MyHDL description
to Verilog: make sure the simulation runs fine first. Although the
converter checks many things and attempts to issue clear error
messages, there is no guarantee that it does a meaningful job unless
the simulation runs fine.
"""

In other words, if the simulation works fine, my goal is to guarantee
that the conversion (if it succeeds) is correct. Otherwise, all bets
are off (even if conversion succeeds).

Note that in this case, a trivial test bench would detect the error,
as q1 in your code cannot have a next attribute.

Miscellaneous remark: please don't use "private" attributes such as
_nrbits. An intbv supports the 'len' function (which returns 0 for
undefined bit widths.)

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
    Using Python as a hardware description language:
    http://jandecaluwe.com/Tools/MyHDL/Overview.html