[myhdl-list] inference problem?

[Haitao Z. <ha...@gm...>]

I could not figure out why the following code could not generate
correct Verilog code (the intermediate q1 is missing):

def reg_dq(clk,d,q):
    def proc():
        while 1:
            yield posedge(clk)
            q.next=d
    return proc()
    
def reg_dq2(clk,d,q):
    if d._nrbits:
        q1=Signal(intbv(0))[d._nrbits:]
    else:
        q1=Signal(intbv(0))
    def proc():
        while 1:
            yield posedge(clk)
            q.next=q1
            q1.next=d
    return proc()        
#    reg1=reg_dq(clk,d,q1)
#    reg2=reg_dq(clk,q1,q)
#    return reg1, reg2

I fail to see the difference between this and the provided examples.
This is just a simple try to generate a delay of 2. The commented out
code didn't work either. I get two assignments to q instead.

Thanks for any help. 

Haitao