[myhdl-list] Re: Verilog Generation issue - fixed signals

[Jan D. <ja...@ja...>]

Jan Decaluwe wrote:
> Frank Palazzolo wrote:
> 
>> So - is it possible to define constant signals within the heirarchy in 
>> general?  I haven't been able to figure out how.  This is actually 
>> pretty ugly, considering that I'd like generic modules at the bottom, 
>> and I'd like to "hardcode" certain parameters on chip, with no 
>> external signals for them outside the chip.
> 

> Another way would be to use assign statements - all synthesis tools
> should understand those.

Follow-up:

In MyHDL 0.4.1, constant signals are implemented using assign
statements. Also, such "undriven" signals now generate a
warning, but no longer an error.

Regards, Jan

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