[myhdl-list] MyHDL plans update

[Jan D. <ja...@ja...>]

Hi all:

As I have just completed a full-time consultancy assignment,
I will have some more time to work on MyHDL in the near term.

One thing I'm working on is a maintenance release (0.4.1) which
should address all points that have been raised in the past months,
and fix the known bugs.

In terms of new features: I've come to the conclusion that a
link to modelsim Verilog and VHDL would be the best way to
increase the awareness and usefulness of MyHDL.

I ordered many modelsim licenses in a previous life :-( but
currently I have no access to modelsim. So I wonder if anyone
out there can help. In the ideal case, I would have ssh access
to a language neutral modelsim at the command line (GUI not
needed), with Verilog VPI and VHDL PLI support, and to the
VPI and PLI documentation, on a Linux (or Unix) platform.

Note that the free versions in a Xilinx webpack don't include
VPI and PLI support, so they are not helpful.

Obviously, the only thing I would do with the tool is
to develop an open sourced link to MyHDL, so the usage time
would be extremely limited.

Best regards,

Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
    Python is fun, and now you can design hardware with it:
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