[myhdl-list] Re: always_comb / signal array
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From: Jan D. <ja...@ja...> - 2004-11-22 21:17:04
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David Brochart wrote: > It seems that "always_comb" doesn't work when an input is an array of signals, Yep, always_comb is intended to emulate a similar "low level" facility in SystemVerilog. It has to inspect the source to find out with signals are used as inputs and which as outputs, and infer the sensitivity list automagically. It does this by inspecting how a certain signal name is used in the code. To support more complex things likes arrays of signals, all kinds of new complexities would have to be taken into account - inspecting indices and slices to see which parts of the array are used as input. In the general case (variable indices) this cannot even be decided. So I think it will remain a low-level facility to describe combinatorial logic based on input signals, as in Verilog. Regards, Jan -- Jan Decaluwe - Resources bvba - http://jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Python is fun, and now you can design hardware with it: http://jandecaluwe.com/Tools/MyHDL/Overview.html |