[myhdl-list] Re: VCD generation bug

[Jan D. <ja...@ja...>]

David Brochart wrote:
> There is a bug in the generation of the VCD file. In the following example:
> 
> ---------------------------------------------------------------------------
> 
> from myhdl import intbv, Signal, Simulation, delay, traceSignals
> 
> def gen(a):
>     while 1:
>         a.next = 0
>         yield delay(10)
>         a.next = 1
>         yield delay(10)
> 
> def dummy(a):
>     b = Signal(intbv(0))
>     b_i0 = gen(b)
>     return b_i0
> 
> def test():
>     a = Signal(intbv(0))
>     a_i0 = gen(a)
>     dummy_i0 = dummy(a)
>     return a_i0, dummy_i0
> 
> test = traceSignals(test)
> sim = Simulation(test)
> sim.run(100)
> 
> ---------------------------------------------------------------------------
> 
> You can see in the generated VCD file that several signals have the same
> identifier. 

There are 2 signals, so there should be two different identifiers,
right? That's also what I see in the VCD definition area, so I'm not sure 
there's a problem here.

> Also, signals in "a_i0" are not traced.

Yes, there was a bug in _extractHierarchy.py. Attached the current version
that probably solves it. (As I had solved this already some time ago, I
think it's about time I'll do a maintenance release...)

Jan

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