[myhdl-list] Re: always_comb problem

[Jan D. <ja...@ja...>]

David Brochart wrote:
> I think this is a good solution indeed, it would work for "always_comb" and
> "toVerilog".
> 
> Thanks,
> 
> David.
> 

The following code in the _SigNameVisitor class in the _always_comb.py file
detecs an 'if __debug__' template, and skips it:

    def visitIf(self, node):
        if len(node.tests) == 1 and not node.else_:
            test = node.tests[0][0]
            if isinstance(test, compiler.ast.Name) and \
               test.name == '__debug__':
                return # skip
        for n in node.getChildNodes():
            self.visit(n)

The complete patched file is attached. It's in my development tree,
but not yet in the Verilog conversion code.

Remarks:

- only a simple template with a single 'if __debug__' test is detected.
More complicated expressions, or if statements with elsifs or else's
are not considered. This might be confusing, but on the other hand
I don't see the usefulness of using the __debug__ variable in more
complex ways than in a single test.

- a more sophisticated method would be possible: check the value of
an arbitrary name (not just __debug__) to see if it is False. This
would permit to turn this variable on or off by user-controlled code.
This is possible but requires a name lookup in the scope of the
function. I'm thinking to implement this as a general solution.

Regards,

Jan

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