[myhdl-list] VCD generation bug

[David B. <dav...@fr...>]

There is a bug in the generation of the VCD file. In the following exampl=
e:

-------------------------------------------------------------------------=
--

from myhdl import intbv, Signal, Simulation, delay, traceSignals

def gen(a):
    while 1:
        a.next =3D 0
        yield delay(10)
        a.next =3D 1
        yield delay(10)

def dummy(a):
    b =3D Signal(intbv(0))
    b_i0 =3D gen(b)
    return b_i0

def test():
    a =3D Signal(intbv(0))
    a_i0 =3D gen(a)
    dummy_i0 =3D dummy(a)
    return a_i0, dummy_i0

test =3D traceSignals(test)
sim =3D Simulation(test)
sim.run(100)

-------------------------------------------------------------------------=
--

You can see in the generated VCD file that several signals have the same
identifier. Also, signals in "a_i0" are not traced.

Regards,

David.