[myhdl-list] Re: always_comb problem

[Jan D. <ja...@ja...>]

David Brochart wrote:
> Thanks for the explanation. I use "print" statements as debug functions but I
> could as well use graphical functions if I do signal processing. In other words
> in this example the problem was caused by "print" but it could be anything that
> is not a signal or variable affectation. Then your solution doesn't work.
> Rather than adding a "pass" for everything we want to skip, we should only
> "keep" the signal/variable affectations and "pass" everything else. Is there a
> way to do that?

Well, there may be an easy way to do this provided
there is some explicit help from the user.

Actually there is a similar problem with conversion to
Verilog: sometimes one would like to add code (e.g.
for debug) that should be "hidden" from conversion (e.g.
because it contains non-convertible constructs.)

A clean way to support this would be to use Python's
prefined __debug__ variable. (This is true by default,
and false when python is invoked with optimizations.)

All code below an "if __debug__:" could simply be
ignored (for always_comb and also conversion.) So this
would be a general way for a user to add arbitrary code,
but of course he would have to state this explicitly.
But, as Explicit Is Better Than Implicit this may not
even be a disadvantage. Note that the actual value
of __debug__ would not be taken into consideration.

What do you think?

Regards, Jan

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