[myhdl-list] Re: always_comb problem

[Jan D. <ja...@ja...>]

David Brochart wrote:
> Hello,
> 
> In the following code:
> 
> --------------------------------------------------------------------------
> 
> from myhdl import intbv, Signal, Simulation, instances, delay, always_comb
> 
> def test(a, b):
>     c = intbv(2)
>     def testFunc():
>         b.next = a.val + c
>         print b.val, a.val
>     return always_comb(testFunc)
> 
> def a_gen(a):
>     while 1:
>         yield delay(10)
>         a.next = a.val + 1
> 
> def top():
>     a = Signal(intbv(0))
>     b = Signal(intbv())
>     test_i = test(a, b)
>     a_gen_i = a_gen(a)
>     return instances()
> 
> 
> top_inst = top()
> sim = Simulation(top_inst)
> sim.run(100)
> 
> --------------------------------------------------------------------------
> 
> It seems that the "always_comb" function doesn't like the "print" in the "test"
> function. 

Correct. Here's the background:

always_comb inspects source code to see how signals are used. It flags "inout"
usage as an error. Normally this is what you want (to get combinatorial semantics),
but it may be too severe on "innocent" cases, as in this case.

For those interested, I'll explain how this happens in the myhdl source code,
as well as the solution. Source inspection occurs by traversing an abstract
syntax tree, generated using the Python compiler package. See class _SigNameVisitor
in the file myhdl/_always_comb.py. Adding the follows methods solves this problem
by avoiding that the traversal proceeds through print statements:

class _SigNameVisitor(object):
    ....
    ....

    def visitPrintnl(self, node):
        pass # skip

    def visitPrint(self, node):
        pass # skip

If have implemented this patch in my development tree, and the resulting
file is attached.

> If I use the "while 1 - yield" structure it works fine, but it would
> be nice to be able to use "always_comb" and still be able to insert debug
> functions inside the code.

But isn't it confusing that you will not necessarily see the resulting
output value at the correct time (as the generator is not sensitive
to the output signal)?

Regards, Jan

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