[myhdl-list] Re: Verilog Generation issue - fixed signals
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From: Jan D. <ja...@ja...> - 2004-09-02 20:25:12
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Frank Palazzolo wrote: > So - is it possible to define constant signals within the heirarchy > in general? I haven't been able to figure out how. This is actually > pretty ugly, considering that I'd like generic modules at the bottom, > and I'd like to "hardcode" certain parameters on chip, with no > external signals for them outside the chip. (Sorry for the delayed response.) While generating Verilog, I can infer which internal signals are not driven by others, and I deliberately chose to flag this as an error (taking into consideration that the intent to go to Verilog is likely synthesis and implementation). This may have been a step too far. In the future, it may be better to flag the issue as a warning instead of an error. In addition, I would have to make sure that the reg gets the proper initial value. One way would be at declaration time: reg [1:0] numchan = 3; # currently the initialization is not there However, I don't know whether this is "synthesizable" in general. Also, the semantics are ambiguous (it looks like initialization, but in some simulators an event from x to 3 will be created.) Another way would be to use assign statements - all synthesis tools should understand those. Regards, Jan -- Jan Decaluwe - Resources bvba - http://jandecaluwe.com Losbergenlaan 16, B-3010 Leuven, Belgium Python is fun, and now you can design hardware with it: http://jandecaluwe.com/Tools/MyHDL/Overview.html |