Re: [myhdl-list] Re: python list of signals

[Tom D. <td...@di...>]

Jan,

Thanks, that worked fine.

Jan Decaluwe wrote:

>
>
> This doesn't mean that you can't use lists of signals - the trick is to
> make sure to use them only during "elaboration". In other words, the
> restrictions to Verilog conversion only apply to the things at the
> lowest level - the generators. At the higher levels of the hierarchy,
> where you use plain functions, you have a lot of freedom, because
> the hierarchy is "elaborated" by the interpreter before conversion.


Thanks, that works fine.

Tom