Re: [myhdl-list] python list of signals

[Tom D. <td...@di...>]

Frank,

Tried that with the same results. I'm sure there is an easy way to do 
this...

Tom


Frank Palazzolo wrote:

>>I was trying to make a variable pipeline module with the following code:
>>
>>def pipe(q, d, clk, stages=1):
>>    
>>
>
>Does it work if you take stages out of the function signature?  It may be
>that the Verilog generation assumes it is a Signal if it's in the
>signature..?
>
>Just a guess...
>-Frank
>
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