RE: [myhdl-list] python list of signals

[Frank P. <pal...@co...>]

>I was trying to make a variable pipeline module with the following code:
>
>def pipe(q, d, clk, stages=1):

Does it work if you take stages out of the function signature?  It may be
that the Verilog generation assumes it is a Signal if it's in the
signature..?

Just a guess...
-Frank