[myhdl-list] python list of signals

[Tom D. <td...@di...>]

I was trying to make a variable pipeline module with the following code:

def pipe(q, d, clk, stages=1):
    """ pipe block
   
    q      -- output, delayed d by stages pipe delays
    d      -- input
    clk    -- clock input
    stages -- number of pipeline delays, 0 is no pipes
    """
    qReg = [Signal(intbv(0,0,q.max)) for i in range(stages)]
    while 1:
      if stages == 0 :
        yield d
        q.next = d
      else :
        yield posedge(clk)
        if stages == 1 :
          q.next = d
        else :
          qReg[0].next = d
          q.next = qReg[stages-2]
          for i in range(stages-2) :
            qReg[i+1].next = qReg[i]

It simulates fine but the list of signals (qReg[]) isn't liked by the 
Verilog converter.

stages is meant to be a compile time parameter and I would like to make 
a variable number of signals based upon its value. Then easily use them 
else where in the module.

If indeed this can't be converted, is there a simple way to accomplish this.

Thanks,
Tom Dillon