[myhdl-list] Verilog Generation issue - fixed signals

[Frank P. <pal...@co...>]

Hello All,

Ok, I've sorted out my issue with Verilog Generation.  Sorry for the 
rather confused previous messages. :)

It turns out that my problem has to do with "Fixed" Signals, i.e. 
Signals which are defined like...

s = Signal(bool(0))

..which are used, but never set beyond initialization.

At the outermost level, these always seem to work.  You can set them 
in the testbed function and forget them, if you want.  I'm guessing 
that this is because they are defined outside the toVerilog() 
statement.  My problems show up if I try to use these at other levels 
of the heirarchy.

Inside of a generator, these always fail with "Can't infer variable 
type".  Granted, it's not too useful to use these inside of a 
generator, since it's not really a "Signal", so this isn't really a 
big deal.  It is a bit of a strange message, however.

The common case I am having trouble with is when you use one in a 
intermediate level, as in this oversimplified example...

def or_gate(a,b,c):
	while 1:
		yield a,b
		c = a | b

def my_bundle(p,q):
	x = Signal(bool(0))
	gen_or = or_gate(p,x,q)
	return instances()
		   
This fails with "signal is not driven".  I can get away with defining 
x = bool(0) in some cases.  However, in the general case this leads 
to another failure - because you can't yield on a non-signal. :(

So - is it possible to define constant signals within the heirarchy 
in general?  I haven't been able to figure out how.  This is actually 
pretty ugly, considering that I'd like generic modules at the bottom, 
and I'd like to "hardcode" certain parameters on chip, with no 
external signals for them outside the chip.

Thanks for any ideas,
Frank