[myhdl-list] Re: Explicit local state and verilog generation

[Jan D. <ja...@ja...>]

Frank Palazzolo wrote:
> A small follow-up...  I realized later that my issue is really about
> type-definition, not state.  I want to bundle internal signal types along
> with a subsystem, and still be able to use verilog generation.  But I'm not
> sure which way is part of the convertable subset, if any.

Again, please send me a relevant example that fails.

Regards, Jan

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