[myhdl-list] Re: Explicit local state and verilog generation

[Jan D. <ja...@ja...>]

Frank Palazzolo wrote:
> Hello,
> 
> I have an application which is doing something strange, and I'm wondering if
> it's my problem or MyHDL.  I am having problems with the verilog generation,
> not with simulation.
> 
> Let me explain via simplified examples:
> 
> Up until now, if I had explicit state inside a sequential logic block, I
> would define it at the outermost level.  So my generator looks like this:
> 
> def mycounter(clk,inbit,outbit,state):
> 	yield 1:
> 		if posedge(clk):
> 			if state < 12:
> 				state.next = state + 1
> 			else:
> 				state.next = 0
> 			outbit.next = state.next[4]

I assume the 'yield' should be 'while', and 'if posedge' should
be 'yield posedge'.

> State is defined outside, as I am not able to place it in the generator (for
> Verilog), though I would like to hide it.

Wait a moment - I don't follow this reasoning. Plain variables can also
contain state, and can be converted to Verilog. For example, the
following should work:

def mycounter(clk,inbit,outbit):
    state = intbv(0)[5:]
    while 1:
        yield posedge(clk)
        if state < 12:
            state += 1
        else:
            state[:] = 0
        outbit.next = state[4] # warning: will now have a clock cycle less delay

MyHDL makes the distinction between variables and signals (as VHDL, unlike
Verilog, but as it should be), but supports these in conversion by using
blocking vs. unblocking assignments appropriately. (Great, isn't it :-))

> So, I am using this technique instead:
> 
> def counter_with_state(clk,inbit,outbit):
> 	state = Signal(intbv(0,min=0,max=16)
> 	inst = mycounter(clk,inbit,outbit,state)
> 	return instances()
> 
> This bundles the state with the generator.  This seems to work for all cases
> in simulation, and in trivial ones with verilog generation.  However, for
> more complex cases, simulation works but verilog generation fails with
> "Signal is not driven" type errors.
> 
> My question is - is this a legitimate technique for Verilog generation?  If
> so, I have a error or have found a bug.  If not, why not?  Maybe I am
> missing something...

All of the above is possible, but I'll need an failing example (the
smallest possible :-)) to judge.

Regards, Jan

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