[myhdl-list] RE: Explicit local state and verilog generation

[Frank P. <pal...@co...>]

A small follow-up...  I realized later that my issue is really about
type-definition, not state.  I want to bundle internal signal types along
with a subsystem, and still be able to use verilog generation.  But I'm not
sure which way is part of the convertable subset, if any.

Thanks again,
Frank