[myhdl-list] Re: Enhanced Simulation and Verilog Generation with the same generators?

[Jan D. <ja...@ja...>]

Frank Palazzolo wrote:

[Sidenote: it seems you start new topics by replying in an existing thread,
which confuses the thread view. Would it be possible to start new topics
by a fresh new post instead - thanks.]

> Ok, on the heels of my success with the first design, I have something more
> ambitious I'd like to try.  However, I've run into the first problem.
> 
> I'd like to be able to take a design in MyHDL, Simulate it, and generate
> Verilog.  However, the simulation I have in mind has some additional
> functionality - I would like to programmatically track the state information
> in the system during the simulation.  Unfortunately, any way I try to
> introduce this code into the generators, I end up introducing a construct
> that breaks the Verilog-generation rules. :(
> 
> Essentially, I'd like to have code in my generators that is marked as "does
> not apply to Verlog generation". 

Before answering the above: note that Python print statements are converted
into Verilog $display functions and can thus be used for debugging purposes.

Excluding code under parameter control is indeed a useful feature, that is
currently not supported by the convertor. It shouldn't be hard to do, as the
convertor has the required info.

The way to do it would be to check test expressions on if statements
in the first step, and not proceeding with analysis or conversion of the
test body if the test happens to be a (global) name with value False.

The easiest would be to just leave the if-then-else structure intact,
so you would get something like this in Verilog:

   if (0) begin
       // code not converted here
   end
   else ...

This should be OK for synthesis tools - perhaps you could confirm
it's OK for yours and then I'll proceed with implementing this.

Regards, Jan

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