RE: [myhdl-list] Enhanced Simulation and Verilog Generation with the same generators?

[Frank P. <pal...@co...>]

One other note...

I did try two other things.  I can use a global variable to hook in
simulation specific code:

Python code is like this in every generator:
--------------------------------------------

if simulating:
	state.next =3D Report(not state)
else:
	state.next =3D not state.

This turns into an "$if 0" in Verilog, but the Report function is still
expanded and required to be synthesizable.

Then, I tried this - which is the best I can do, using a function =
reference
veriable:
-------------------------------------------------------------------------=
---
---------

def NullFunc(state):
	return state

def ReportFunc(state):
	# some non-synthesizable stuff here
	return state

if simulating:
	Report =3D NullFunc
else:
	Report =3D ReportFunc
...
and then in the generator...
...
	state.next =3D Report(not state)

In this case, The Simulation-Specific version of Report is required to =
to
have a synthesizable signature, but the content of the function can be
whatever you want...because when you synthesize, it will be replaced =
with a
null function.  Almost perfect :)

-Frank