[myhdl-list] Enhanced Simulation and Verilog Generation with the same generators?

[Frank P. <pal...@co...>]

Ok, on the heels of my success with the first design, I have something =
more
ambitious I'd like to try.  However, I've run into the first problem.

I'd like to be able to take a design in MyHDL, Simulate it, and generate
Verilog.  However, the simulation I have in mind has some additional
functionality - I would like to programmatically track the state =
information
in the system during the simulation.  Unfortunately, any way I try to
introduce this code into the generators, I end up introducing a =
construct
that breaks the Verilog-generation rules. :(

Essentially, I'd like to have code in my generators that is marked as =
"does
not apply to Verlog generation".  Here are a couple examples:

    def toggle_ff(clk,q,q_n):
        while 1:
            yield posedge(clk)
            q.next =3D not q
            q_n.next =3D q
		# now report the state change to a global func
            Report(q.next)

I can't use this approach, as the toVerilog() chokes on the call to =
Report()

Here's an attempt to use object-oriented modelling:

class T:
    "Toggle Flip Flop"
    def __init__(self):
        self.state =3D Signal(0)
        self.count =3D 0
    def gen(self,clk,q,q_n):
        while 1:
            yield posedge(clk)
            q.next =3D not q
            q_n.next =3D q
		# log the state change
            self.state =3D q.next
            self.count +=3D 1

Again, the last two lines are fine for simulation, but Verilog =
generation
wont work.

I'm starting to think I need to try some kind of variation on =
conditional
instantiation, based on whether I am simulating or generating Verilog.  =
I
doubt I can do that with a single generator though, because the =
signatures
of the generators would be affected.  It would work if I had two =
versions of
each generator - one for this simulation and one for verilog.=20

Anyways... and all hints appreciated...

Thanks,
Frank