[myhdl-list] Tri-State Logic

[Jan D. <ja...@ja...>]

> Hello,
> 
> Is there a way to represent tri-state logic in MyHDL?

There are two parts to this: first, representation of the tri-state
value, and second, how to model resolution of contributing drivers.

For representation, I believe (in good MyHDL tradition) that Python
has all we need, in that 'None' (no value) is perfectly adequate.

A little advertised feature of a Signal is that you can construct it
with a value None - this is even the default value. To such a Signal,
you can subsequently assign anything of any type - there is no
value type checking as in all other cases.

As to modelling resolution, I'm not inclined to built it into the
language as in Verilog or VHDL. In Verilog, the solution is to
introduce a vast number of keywords. In VHDL, it's done with
resolution functions - complicated and implicit. My thinking
is to support such things through a "standard library" that
models specific resultion behaviors explicitly in generators.

As as sidenote, and based on my ASIC design experience, I believe
tri-states should be avoided on-chip as they always cause all
kinds of tricky problems - normally there are better solutions.

For example, a tristate bus model could look as follows:

class ContentionError(Exception):
    pass

def TristateBus(bus, *drivers):
    """Generic tristate bus model."""
    while 1:
        yield drivers
        actives = [a for a in drivers if a != None]
        if len(actives) > 1:
            raise ContentionError("Multiple active bus activedrivers")
        elif len(actives) == 1:
            bus.next = actives[0]
        else:
            bus.next = None

Note that this works for any number of drivers, by using the fact
that sensitivity lists in MyHDL can be true Python lists - a unique and
very useful feature I believe.

> Also, would it carry-over to the generated Verilog?
> (Forgive me, I don't even know if/how this is done in vanilla 
> Verilog, only in VHDL)

Not at this point.

The way to do it would probably to generate an equivalent Verilog model
for each generator of the "standard library" (see above).

One complication is that for Verilog output, bit widths need to be
defined, but a Signal(None) has no defined bit width. Perhaps the
intbv class should accept 'None' values also - it doesn't do this
at this moment and I would need to think about it further to see
whether that's really a good idea.

> and finally...
> 
> If not, is it a reasonable feature request?

Yes :-)

Regards, Jan

-- 
Jan Decaluwe - Resources bvba - http://jandecaluwe.com
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