[myhdl-list] Tri-State Logic
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From: Frank P. <pal...@co...> - 2004-04-05 04:28:36
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Hello, Is there a way to represent tri-state logic in MyHDL? Also, would it carry-over to the generated Verilog? (Forgive me, I don't even know if/how this is done in vanilla Verilog, only in VHDL) and finally... If not, is it a reasonable feature request? Thanks, Frank |