[myhdl-list] Tri-State Logic

[Frank P. <pal...@co...>]

Hello,

Is there a way to represent tri-state logic in MyHDL?

Also, would it carry-over to the generated Verilog?
(Forgive me, I don't even know if/how this is done in vanilla 
Verilog, only in VHDL)

and finally...

If not, is it a reasonable feature request?

Thanks,
Frank