Re: [myhdl-list] Re: MyHDL success

[bedros <be...@ya...>]

--- Jan Decaluwe <ja...@ja...> wrote:
> bedros wrote:
> > agree, Jan did a great job on MyHDL. I've been
> using
> > it for several months now to verify my ideas
> before
> > start coding in VHDL.
> 
> Excellent, that's exactly what MyHDL usage should be
> all
> about. Now, the VHDL coding, is that for synthesis?
> If
> it is, would Verilog (and therefore conversion from
> MyHDL
> code to Verilog) be an option instead?

my design would be integrated with other VHDL designs,
so I'll stay with VHDL for now. The design is fairly
complex and would be synthesised into FPGA. 

The reason I decided to build a complete model of the
project in MyHDL is to explore different
architectures. Python makes it easy to build data
structures with very little effort. 

I never tried trace.py. However, coverage.py is very
easy to use and gives a list of statements that are
not got executed. Helps a lot fine tuning my test
cases

-Bedros

> > I also got it to work with code coverage utility
> > (coverage.py)
> 
> Good to hear. Does this work better than trace.py?
> I haven't use any of the two, but I noticed that
> trace.py
> is a standard (though undocumented) unlibrary
> module.
> 
> Regards, Jan
> 
> -- 
> Jan Decaluwe - Resources bvba -
> http://jandecaluwe.com
> Losbergenlaan 16, B-3010 Leuven, Belgium
>     Python is fun, and now you can design hardware
> with it:
>     http://jandecaluwe.com/Tools/MyHDL/Overview.html
> 
> 
> 
>
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