Re: [myhdl-list] Re: MyHDL success
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jandecaluwe
From: <ma...@cr...> - 2004-04-01 18:23:28
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Hello Jan, Frank, and MyHDL frieds, Comments in Verilog are needed to embed physical design constraints into a design, such as for FPGA realization with high performance; these are called metacomments. I do this now, using Python code to create computer generated designs which have everything locked down and placed as structural Verilog, essentially "linked" to a Virtex-II or Virtex-II Pro primitives library. Now, having said all this, there is also a new standard representation for constraints and attributes in Verilog, without the metacomment scheme. Icarus Verilog uses this today now, as does several other synthesis tools. It looks something like this: (* RLOC_ORIGIN = X0Y0 *) I personally do not like this style of compiler hinting for synthesis, but Steve Williams (who maintains Icarus) assures me this is much better for everyone. My issue is that I think comments are more useful as they're passively inferred, without disturbing the semantics of the appertaining Verilog -- only the implementation is effected for synthesis or possibly simulation. I thoroughly dislike the introduction of new syntax to an already "large" language like Verilog. Steve indicates however, that determinating scope and other aspects of inference is much easier on the compiler with the new-style attributes. These form of attributes are admitedly much more standard, which dramatically contrasts with the metacomment scheme, which are all over the map across different tools. In any case, I now use Python to generate very large Verilog designs, via structural code and other performance-oriented constraints, etc. It would indeed be rather important for MyHDL to have the ability to embed attributes, preferrably as both comments and new-style attributes. That way, MyHDL could be used for generation and verification of physical designs that use Verilog as the carrier language for access to physical synthesis tools or for co-simulation. One other question that may arise in this context: Why bundle everything into the Verilog? Can't a constraints "side-file" be used for synthesis, and just ignored for simulation? This is generally true. For example, for the Xilinx implementation tools, user contraints are entered with a UCF "side-file." However, a reason NOT to do this is if you're trying to create a completely self-contained or encapsulated design for subsequent use by another designer; e.g. creating a core. The existence of a "side-file" implies it's continued use with additional synthesis users, and this gets out of hand quickly, esp. if numerous instances of the same core are used in a particular implementation. Having everything self-contained is necessary. MyHDL would be more valuable IMHO if the power of Python can also be applied to generation of physical constraints, so that constraint generation can also be included within the full verification flow that MyHDL otherwise allows. Best, Michael > Frank Palazzolo wrote: > > Jan, > > > > Just wanted to drop a line and say that MyHDL is working great for me! I'm > > doing a CPLD design for a switching power-supply controller, and I just got > > both the simulation and verilog generation working flawlessly. I'm > > targetting the Xilinx XC9536, but testing with a Xilinx SpartanIIE-based > > FPGA board. > > Good to hear. Looks like you're the first one I know of to finish a complete > design to implementation with MyHDL. If you would be interested in writing a > small success story (to put on a website, or post to a newsgroup), let me know. > > > I only ran into one wishlist item. It might be nice to have a mechanism to > > put comments into the generated verilog via python. At first, I thought > > that could mean simply reading the doc information from the generators and > > adding that as comments in the verilog. But, with some of the naming > > changes that occur, that might be confusing. You might want to have some > > kind of dedicated verilog_comment() construct instead. > > Could you comment on exactly what would be the purpose? I see the Verilog > code merely as a back-end format, not necessarily friendly to human readers. > Is it just to recognize where the code came from? Rewriting the doc-string > should be easy. > > Regards, Jan > > -- > Jan Decaluwe - Resources bvba - http://jandecaluwe.com > Losbergenlaan 16, B-3010 Leuven, Belgium > Python is fun, and now you can design hardware with it: > http://jandecaluwe.com/Tools/MyHDL/Overview.html > > > > ------------------------------------------------------- > This SF.Net email is sponsored by: IBM Linux Tutorials > Free Linux tutorial presented by Daniel Robbins, President and CEO of > GenToo technologies. Learn everything from fundamentals to system > administration.http://ads.osdn.com/?ad_id=1470&alloc_id=3638&op=click > _______________________________________________ > myhdl-list mailing list > myh...@li... > https://lists.sourceforge.net/lists/listinfo/myhdl-list > |