RE: [myhdl-list] Re: MyHDL success
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From: Frank P. <pal...@co...> - 2004-04-01 14:32:18
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>Could you comment on exactly what would be the purpose? I see the = Verilog code merely as a back-end format, not necessarily friendly to uman = readers. Is it just to recognize where the code came from? Rewriting the = doc-string should be easy. Right, my design was small enough that it was obvious how the MyHDL = mapped over to the Verilog. I just thought that if the design was bigger, it = would be useful for tracking/debug purposes. Also, I can envision a project = which uses MyHDL-generated Verilog, along with other Verilog or VHDL code from other sources. Documenting the interface to the MyHDL-generated Verilog would probably be most useful in the actual Verilog in this case. Hmmm...if rewriting the doc-string would be easy, maybe there should = just be an option to do that during verilog generation. This would be = sufficient, I think. I'll let you know about the success-story writeup as soon as I get the = full system working :) Oh one other thing...I'm curious where the name MyHDL came from. It = seems there are some academic references to something called PyHDL, which I = would imagine would be the more natural name. It seems like every Python = project starts with Py these days... Thanks, Frank |